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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1999 mos integrated circuit m m m m pd16640c 300/309-output tft-lcd source driver (64 gray scale) data sheet document no. s11269ej1v1ds00 (1st edition) date published june 1999 ns cp (k) printed in japan description the m pd16640c is a source driver for tft-lcd 64-gray scale displays. its logic circuit operates at 3.3 v and the driver circuit operates at 3.3 or 5.0 v (selectable). the input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs g -corrected by the internal d/a converter and 11 external power supplies. the clock frequency is 55 mhz min. by switching over the number of outputs between 300 and 309, the m pd16640c can be used in tft-lcd panels conforming to the svga/xga standards. features cmos level input number of outputs selectable (o sel = h : 300 outputs, o sel = l : 309 outputs) 6 bits (gray scale data) x 3 dots input 64-value output by 11 external power supplies and internal d/a converter output dynamic range : v ss2 + 0.1 v to v dd2 - 0.1 v high-speed data transfer: f max. =55 mhz min.(internal data transfer speed when v dd1 = 3.0 v) precharge-less output buffer level of g -corrected power supply can be inverted. input data inversion function (inv) logic power supply (v dd1 ) : 3.3 v 0.3 v driver power supply (v dd2 ) : 3.3 v 0.3 v (v sel = h) 5.0 v 0.5 v (v sel = l) ordering information part number package m pd16640cn-xxx tcp (tab package) remark the tcps external shape is customized. to order your tcps external shape, please contact a nec salesperson.
data sheet s11269ej1v1ds00 2 m m m m pd16640c 1. block diagram c 1 c 2 c 102 c 103 sthr r,/l clk o sel d 00 - d 05 d 10 - d 15 d 20 - d 25 stb v sel v 0 - v 10 s 1 s 2 s 3 s 309 v ss2 v dd2 (3.3/5.0 v) v ss1 v dd1 (3.3 v) sthl inv 103-bit bidirectional shift register data register latch d/a converter output buffer remark /xxx indicates active low si gnal.
data sheet s11269ej1v1ds00 3 m m m m pd16640c 2. pin configuration ( m m m m pd16640cn-xxx) v sel v ss2 v dd2 v 10 v 8 v 6 s 309 s 308 v 4 v 2 v 0 r,/l d 20 d 21 d 22 d 23 d 24 d 25 stb sthl v dd1 clk v ss1 sthr d 10 d 11 d 12 d 13 d 14 d 15 d 00 d 01 d 02 d 03 d 04 d 05 v 1 v 3 v 5 v 7 v 9 v dd2 v ss2 o sel s 2 s 1 inv copper foil surface s 307 s 3 remark o sel and v sel pins are internally pulled up. therefore, the number of input pins can be reduced by opening or short-circuiting these pins to v ss2 by means of tcp writing.
data sheet s11269ej1v1ds00 4 m m m m pd16640c 3. pin functions pin symbol pin name description s 1 to s 309 driver output output 64 gray scale analog voltages converted from digital signals. o sel = h : 300 outputs (s 1 - s 150 , s 160 - s 309 ) o sel = l : 309 outputs (s 1 - s 309 ) output pins s 151 to s 159 are invalid in 300-output mode. d 00 to d 05 display data input inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (rgb). d 10 to d 15 d x0 : lsb, d x5 : msb d 20 to d 25 r,/l shift direction select input this pin inputs/outputs start pulses in cascade mode. shift direction of shift register is as follows: r,/l = h : sthr input, s 1 ? s 309 , sthl output r,/l = l : sthl input, s 309 ? s 1 , sthr output sthr right shift start pulse i/o r,/l = h : inputs start pulse r,/l = l : outputs start pulse sthl left shift start pulse i/o r,/l = h : outputs start pulse r,/l = l : inputs start pulse o sel number of output selection selects number of outputs. this pin is internally pulled up by v dd1 power supply. o sel = h : 300 outputs o sel = l : 309 outputs v sel driver voltage selection selects driver voltage. this pin is internally pulled up by v dd2 power supply. v sel = h : 300 outputs v sel = l : 309 outputs clk shift clock input inputs shift clock to shift register. display data is loaded to data register at rising edge of this pin. when o sel = h, start pulse output goes high at rising edge of 100th clock after start pulse has been input, and serves as start pulse to driver in next stage. when o sel = l, start pulse output goes high at rising edge of 103rd clock after start pulse has been input, and serves as start pulse to driver in next stage. 103rd clock of driver in first stage serves as start pulse of driver in next stage. stb latch input contents of data register are latched at rising edge, transferred to d/a converter, and output as analog voltage corresponding to display data. contents of internal shift register are cleared after stb has been input. one pulse of this signal is input when m pd16640c is started, and then device operates normally. for stb input timing, refer to 8. switching characteristic waveform. v 0 to v 10 g -corrected power supply inputs g -corrected power from external source. v ss2 +0.1 v v 10 v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 v dd2 - 0.1 v or v ss2 +0.1 v v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 10 v dd2 - 0.1 v maintain gray scale power supply during gray scale voltage output. inv data inversion input input data can be inverted when display data is loaded. inv = h : inverts and loads input data. inv = l : does not invert input data. v dd1 logic circuit power supply 3.3 v 0.3 v v dd2 driver circuit power supply v sel = h : v dd2 = 3.3 v 0.3 v v sel = l : v dd2 = 5.0 v 0.5 v v ss1 logic ground ground v ss2 driver ground ground caution be sure to turn on power in the order v dd1 , logic input, v dd2 , and gray scale power (v 0 to v 10 ), and turn off power in the reverse order, to prevent the m m m m pd16640c from being damaged by latchup. be sure to observe this power sequence even during a transition period.
data sheet s11269ej1v1ds00 5 m m m m pd16640c 4. relation between input data and output voltage value the 11 major points on the g - characteristic curve of the lcd panel are arbitrarily set by external power supplies v 0 through v 10 . if the display data is 00h or 3fh, gray scale voltage v 0 or v 10 is output. if the display data is in the range 01h to 3eh, the high-order 3 bits select an external powers pair v n+1 , v n . the low-order 3 bits evenly divide the range of v n+1, v n into eight segments by means of d/a conversion (however, the ranges from v 9 to v 8 and from v 2 to v 1 are divided into seven segments) to output a 64-grayscale voltage. d x5 (msb) d x4 d x3 d x2 d x1 d x0 (lsb) d x5 d x4 d x3 v n+1 -v n 000 v 1 -v 2 001 v 2 -v 3 010 v 3 -v 4 011 v 4 -v 5 100 v 5 -v 6 101 v 6 -v 7 110 v 7 -v 8 111 v 8 -v 9 v n v n+1 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 d x2 -d x0 high-order 3 bits : g -corrected power selected (v n+1 -v n) low-order 3 bits : 3-bit d/a (range v n -v n+1 is divided into 7 or 8 segments) figure 4-1. relation between input data and g g g g -corrected voltage 0.1 v 0.1 v v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 07f171f input data (hex) 27 2f 37 3f v dd2 v 0 v ss2 v 10 gray scale supply specified by 00h 7 segments 8 segments 8 segments 8 segments 8 segments 8 segments 8 segments 7 segments gray scale supply specified by 3fh
data sheet s11269ej1v1ds00 6 m m m m pd16640c table 4-1. relation between input data and output voltage input data d x5 d x4 d x3 d x2 d x1 d x0 output volta g e 00h 000000v 0 01h 000001 v 2 + ( v 1 C v 2 ) 6/7 02h 000010 v 2 + ( v 1 C v 2 ) 5/7 03h 000011 v 2 + ( v 1 C v 2 ) 4/7 04h 000100 v 2 + ( v 1 C v 2 ) 3/7 05h 000101 v 2 + ( v 1 C v 2 ) 2/7 06h 000110 v 2 + ( v 1 C v 2 ) 1/7 07h 000111v 2 08h 001000 v 3 + ( v 2 C v 3 ) 7/8 09h 001001 v 3 + ( v 2 C v 3 ) 6/8 0ah 001010 v 3 + ( v 2 C v 3 ) 5/8 0bh 001011 v 3 + ( v 2 C v 3 ) 4/8 0ch 001100 v 3 + ( v 2 C v 3 ) 3/8 0dh 001101 v 3 + ( v 2 C v 3 ) 2/8 0eh 001110 v 3 + ( v 2 C v 3 ) 1/8 0fh 001111v 3 10h 010000 v 4 + ( v 3 C v 4 ) 7/8 11h 010001 v 4 + ( v 3 C v 4 ) 6/8 12h 010010 v 4 + ( v 3 C v 4 ) 5/8 13h 010011 v 4 + ( v 3 C v 4 ) 4/8 14h 010100 v 4 + ( v 3 C v 4 ) 3/8 15h 010101 v 4 + ( v 3 C v 4 ) 2/8 16h 010110 v 4 + ( v 3 C v 4 ) 1/8 17h 010111v 4 18h 011000 v 5 + ( v 4 C v 5 ) 7/8 19h 011001 v 5 + ( v 4 C v 5 ) 6/8 1ah 011010 v 5 + ( v 4 C v 5 ) 5/8 1bh 011011 v 5 + ( v 4 C v 5 ) 4/8 1ch 011100 v 5 + ( v 4 C v 5 ) 3/8 1dh 011101 v 5 + ( v 4 C v 5 ) 2/8 1eh 011110 v 5 + ( v 4 C v 5 ) 1/8 1fh 011111v 5 20h 100000 v 6 + ( v 5 C v 6 ) 7/8 21h 100001 v 6 + ( v 5 C v 6 ) 6/8 22h 100010 v 6 + ( v 5 C v 6 ) 5/8 23h 100011 v 6 + ( v 5 C v 6 ) 4/8 24h 100100 v 6 + ( v 5 C v 6 ) 3/8 25h 100101 v 6 + ( v 5 C v 6 ) 2/8 26h 100110 v 6 + ( v 5 C v 6 ) 1/8 27h 100111v 6 28h 101000 v 7 + ( v 6 C v 7 ) 7/8 29h 101001 v 7 + ( v 6 C v 7 ) 6/8 2ah 101010 v 7 + ( v 6 C v 7 ) 5/8 2bh 101011 v 7 + ( v 6 C v 7 ) 4/8 2ch 101100 v 7 + ( v 6 C v 7 ) 3/8 2dh 101101 v 7 + ( v 6 C v 7 ) 2/8 2eh 101110 v 7 + ( v 6 C v 7 ) 1/8 2fh 101111v 7 30h 110000 v 8 + ( v 7 C v 8 ) 7/8 31h 110001 v 8 + ( v 7 C v 8 ) 6/8 32h 110010 v 8 + ( v 7 C v 8 ) 5/8 33h 110011 v 8 + ( v 7 C v 8 ) 4/8 34h 110100 v 8 + ( v 7 C v 8 ) 3/8 35h 110101 v 8 + ( v 7 C v 8 ) 2/8 36h 110110 v 8 + ( v 7 C v 8 ) 1/8 37h 110111v 8 38h 111000 v 9 + ( v 8 C v 9 ) 6/7 39h 111001 v 9 + ( v 8 C v 9 ) 5/7 3ah 111010 v 9 + ( v 8 C v 9 ) 4/7 3bh 111011 v 9 + ( v 8 C v 9 ) 3/7 3ch 111100 v 9 + ( v 8 C v 9 ) 2/7 3dh 111101 v 9 + ( v 8 C v 9 ) 1/7 3eh 111110v 9 3fh 111111v 10
data sheet s11269ej1v1ds00 7 m m m m pd16640c 4.1 g g g g -corrected power circuit the reference power supply of the d/a converter consists of a ladder circuit with a total of 64 resistors, and resistance s ri between g -corrected power pins differs depending on each pair of g -corrected power pins. one pair of g -corrected power pins consists of seven or eight series resistors, and resistance s ri in the figure below is indicated as the sum of the seven or eight resistors. the resistance ratio between the g -corrected power pins ( s ri ratio) is designed to be a value relatively close to the ratio of the g -corrected voltages v 1 to v 9 (gray-scale voltages in 8 steps) used in an actual lcd panel. under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the g -corrected power supplies and the gray-scale voltages in 8 steps of the resistor ladder circuits of the m pd16640c, and no current flows into the g -corrected power pins v 1 to v 9 . as a result, a voltage-follower circuit is not necessary. figure 4-2. g g g g -corrected power circuit v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 8 v 9 v 10 i 0 r 0 = 2.39 k w pd16640c r 1 = s r i = 4.45 k w i 1 i 2 i 3 i 4 i 5 i 6 i 7 i 8 i 9 i 10 7 i = 1 r 2 = s r i = 6.19 k w 8 i = 1 r 3 = s r i = 3.58 k w 8 i = 1 r 4 = s r i = 2.15 k w 8 i = 1 r 5 = s r i = 2.03 k w 8 i = 1 r 6 = s r i = 1.61 k w 8 i = 1 r 7 = s r i = 2.03 k w 8 i = 1 r 8 = s r i = 3.39 k w 7 i = 1 r 9 = 2.55 k w m g -corrected power pin g -corrected resistor sum of eight g -corrected resistors - + - + - + - + - + - + - + - + - + - + - +
data sheet s11269ej1v1ds00 8 m m m m pd16640c 5. relationship between input data and output pin data format : 6 bits x rgb(3 dots) input width : 18 bits (1) r,/l = h (right shift) output s 1 s 2 s 3 ? s 308 s 309 data d 00 to d 05 d 10 to d 15 d 20 to d 25 ? d 10 to d 15 d 20 to d 25 (2) r,/l = l (left shift) output s 1 s 2 s 3 ? s 299 s 300 data d 00 to d 05 d 10 to d 15 d 20 to d 25 ? d 10 to d 15 d 20 to d 25 6. operation of output buffer the output buffer consists of an operational amplifier circuit that does not perform precharge operation. therefore, driver output current i voh1/2 is the charging current to the lcd, and i vol1/2 is the discharging current. figure 6-1. lcd panel driving waveform (i vol1/2 /i voh1/2 ) write (i vol1/2 /i voh1/2 ) v dd2 s n v ss2 write 1 horizontal period
data sheet s11269ej1v1ds00 9 m m m m pd16640c 7. electrical specifications absolute maximum ratings (v ss1 = v ss2 = 0 v) parameter symbol ratings unit logic power supply v dd1 C0.3 to +4.5 v driver power supply v dd2 C0.3 to +6.0 v input voltage v i C0.3 to v dd1,2 + 0.3 v output voltage v o C0.3 to v dd1,2 + 0.3 v operating ambient temperature t a C10 to +75 c storage temperature t stg C55 to +125 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range (t a = C10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic supply voltage v dd1 3.0 3.3 3.6 v driver supply voltage v dd2 v sel = h 3.0 3.3 3.6 v v sel = l 4.5 5.0 5.5 v high-level input voltage v ih r,/l, clk, stb, o sel , v sel, 0.7v dd1 v dd1 v low-level input voltage v il sthr(sthl), d 00 -d 05 ,d 10 -d 15 , d 20 -d 25 00.3v dd1 v g -corrected supply voltage v 0 -v 10 v ss2 +0.1 v dd2 - 0.1 v maximum clock frequency f max. 55 mhz
data sheet s11269ej1v1ds00 10 m m m m pd16640c electrical characteristics (t a = C10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 3.3 v 0.3 v or 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leakage current i il d 00 -d 05 , d 10 -d 15 , d 20 -d 25 , r,/l, stb 1.0 m a pull-up resistor r pu v dd1 = 3.3 v, o sel , v sel 40 100 250 k w high-level output voltage v oh sthr(sthl),i o = - 1.0 ma v dd1 - 0.5 v low-level output voltage v ol sthr(sthl),i o =+1.0 ma 0.5 v static current consumption of i vn1 v dd1 =3.3 v v 0 -v 1 105 210 420 m a g -corrected supply current v n - v n+1 =0.5 v v 1 -v 2 56 113 226 m a (v dd2 = 3.3 v or 5.0 v ) v 2 -v 3 41 82 164 m a v 3 -v 4 70 140 280 m a v 4 -v 5 117 234 468 m a v 5 -v 6 124 248 496 m a v 6 -v 7 156 313 626 m a v 7 -v 8 124 248 496 m a v 8 -v 9 74 149 298 m a v 9 -v 10 99 198 396 m a driver output current (v dd2 = 3.3 v) i voh1 v out =2.7 v, v x =3.2 v note1 v dd1 =v dd2 =3.3 v - 0.16 - 0.08 ma i vol1 v out =0.6 v, v x =0.1 v note1 v dd1 =v dd2 =3.3 v 0.07 0.14 ma driver output current (v dd2 = 5.0 v) i voh2 v out =4.4 v, v x =4.9 v note1 v dd1 =3.3 v, v dd2 =5.0 v - 0.24 - 0.12 ma i vol2 v out =0.6 v, v x =0.1 v note1 v dd1 =3.3 v, v dd2 =5.0 v 0.10 0.20 ma output voltage deviation d v o v dd1 =3.3 v, v dd2 =3.3 v or 5.0 v, v out = 0.5 v,1.5 v, 2.5 v note1 10 20 mv output voltage deviation d v p-p input data 5mv output voltage range v o input data : 00h to 3fh v ss2 + 0.1 v dd2 - 0.1 v dynamic logic current consumption i dd1 no load note2 0.5 2.5 ma dynamic driver current consumption i dd21 no load, v dd2 =3.3 v note2 3.0 10 ma i dd22 no load, v dd2 =5.0 v note2 3.0 10 ma notes 1. v x is output voltage of analog output pins s 1 to s 309 . v out is the voltage applied to analog output pins s 1 to s 309 . 2. the stb cycle is specified at 31 m s and f clk = 16 mhz.
data sheet s11269ej1v1ds00 11 m m m m pd16640c switching characteristics (t a = - - - - 10 to +75 c, v dd1 = 3.3 v 0.3 v, v dd2 = 3.3 v 0.3 v or 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 15 pf 7 12 ns t phl1 712ns driver output delay time t plh21 v dd2 =3.3 v v o :0.1 v 2.6 m s t plh31 2 k w +75 pf x 2 ? 3.2 v 3.0 10 m s t phl21 v o :3.2 v 2.4 m s t phl31 ? 0.1 v 3.2 10 m s driver output delay time t plh22 v dd2 =5.0 v v o :0.1 v 2.2 m s t plh32 2 k w +75 pf x 2 ? 4.9 v 2.9 10 m s t phl22 v o :4.9 v 2.6 m s t phl32 ? 0.1 v 3.6 10 m s input capacitance c i1 sthr(sthl), t a =25 c1020pf c i2 v 0 -v 10 , t a = 25 c 60 100 pf c i3 sthr(sthl), other than v 0 -v 10 , t a =25 c 10 15 pf timing requirements (t a = - - - - 10 to +75 c, v dd1 = 3.3 v 0.3 v, v ss1 = 0 v, t r = t f = 3.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 18 ns clock pulse high period pw clk (h) 4ns clock pulse low period pw clk (l) 4ns data setup time t setup1 4ns data hold time t hold1 0ns start pulse setup time t setup2 4ns start pulse hold time t hold2 0ns inv setup time t setup4 4ns inv hold time t hold4 0ns start pulse low period t spl 2clk start pulse rise time t spr1 o sel =h 100 clk t spr2 o sel =l 103 clk final data timing t setup3 1clk clk-stb time t inv 1clk stb-clk time t ldt 1clk time between stb and start pulse t clk-stb clk -? stb - 7ns stb-pol time t stb-clk stb - ? clk - 7ns
data sheet s11269ej1v1ds00 12 m m m m pd16640c 8. switching characteristic waveform(r,/l= h) unless otherwise specified, the input level is defined to v ih = 0.7 v dd1 , v il = 0.3 v dd1 . t setup2 d n0 - d n5 v out clk sthr (1st dr.) sthl (1st dr.) stb t hold1 t setup1 t plh1 t setup3 t r 90% 10% t inv v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 t hold2 pw clk(l) pw clk t spl t f 1 d 1 - d 3 d 1 - d 3 d 4 - d 6 d 304 - d 306 d 307 - d 309 d 310 - d 312 d 3067 - d 3069 d 3070 - d 3072 d 4 - d 6 1024 1025 2 104 105 3 12 103 invalid invalid t clk-stb pw clk(h) t spr1/2 t ldt hi-z t plh31/32 target voltage 0.1 v dd2 6-bit accuracy t plh21/22 t phl31/32 t phl21/22 1023 d 3064 - d 3066 t phl1 inv t setup4 v dd1 v ss1 invalid invalid t hold4 t stb-clk
data sheet s11269ej1v1ds00 13 m m m m pd16640c 9. recommended mounting conditions the following conditions must be met for mounting conditions of the m pd16640c. for more details, refer to the semiconductor device mounting technology manual(c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. m pd16640cn- xxx : tcp(tab pack age) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 sec ; pressure 100g(per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c ; pressure 3 to 8 kg/cm 2 ; time 3 to 5 sec. real bonding 165 to 180 c pressure 25 to 45 kg/cm 2 time 30 to 40secs(when using the anisotropy conductive film sumizac1003 of sumitomo bakelite,ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s11269ej1v1ds00 14 m m m m pd16640c [memo]
data sheet s11269ej1v1ds00 15 m m m m pd16640c notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd16640c reference documents nec semiconductor device reliability/quality control system(c10983e) quality grades to necs semiconductor devices(c11531e) the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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